Roy Akber, CEO, RUSH PCB
When designing an RF circuit, one must choose the most appropriate Printed Circuit Board (PCB) material for the application. In this context, modern Computer Aided Engineering (CAE) simulation tools help engineers by predicting the electrical performance of circuits on different types of PCB materials. These tools use material parameters in their calculations, with relative dielectric constant being one of the most important. But most such tools overlook an equally important material parameter during the design process, i.e., the surface roughness of the conductor. Contrary to popular opinion, the conductor surface is never perfectly smooth, and this has consequences in high-frequency circuit design.
PCB manufacturers including Rush PCB Inc. understand the effects of conductor surface roughness on circuit performance. In fact, scientists have since long studied the effect of grooves present on the surface of a conductor, having noted the additional losses through the conductors caused by them. In worst-case scenarios, the grooves cause losses that sometimes reached a factor of two. The explanation proposed was that electromagnetic (EM) waves travel mostly along the surface of a conductor, e.g., the copper signal trace. The grooves effectively cause the signal paths to become longer, as the EM waves, while traveling along the surface, have to enter into, and then exit out of the grooved shapes.
The surface roughness of a conductor thus creates a longer mean path, resulting in additional losses. Effectively, the higher the degree of conductor surface roughness, the higher will be the resistance from skin-depth effects. When an EM wave propagates through a conductor, this ‘skin effect’ tends to change the current distribution of the EM wave to concentrate more towards the surface of the conductor rather than remaining deep within the conductor material.
When using EM simulators or other commercial CAE tools, designers account for the effects of conductor surface roughness by relying on the traditional Morgan Correlation. They do this by applying a surface-roughness correction factor, Kr, which is a numerical factor based on the ratio of a smooth surface to a rough one. While calculating the loss of high-frequency microstrip lines, using the Kr factor does a good job of closely matching the measured results for conductor losses. However, there are cases in which both predictions and measurements fail to match as closely as one might wish.
Such deviations between the calculated and the measured values can be expensive at the design stage, especially since achieving the desired performance specifications can lead to additional design iterations. Avoiding such delays in design might mean considering carefully the choice of an RF PCB laminate in terms of its conductor’s surface roughness.
Types of Copper Cladding
Manufacturers must use some form of a copper conductor cladding on the PCB substrate. Three types are most common; rolled-annealed (RA) copper, electrodeposited (ED) copper, and reverse-treated (RT) copper.
Forming RA copper foils involves rolling the copper ingot through a rolling mill, where subsequent passes through the rollers results in a thin copper foil with good thickness consistency.
ED copper formation requires depositing copper onto a slowly-rotating, polished stainless-steel drum, within a bath containing a solution of copper sulfate. While the surface roughness of the copper where it meets the stainless-steel drum is similar to that of RA copper, the copper surface of the deposition side facing the solution is much rougher.
RT foil production begins by plating the ED copper foil on the drum side, when the foil on the bath side is still low profile.
Since the copper foil must adhere to the dielectric material, which might range from FR-4 to polytetrafluoroethylene (PTFE) substrates, the copper surface must be treated to increase its adhesion. This is because a perfectly smooth copper surface does not adhere ideally to the dielectric. Whether formed by the RA or ED processes, an untreated copper film has a surface typically covered with tiny tooth-like imperfections, and the jagged surface is ideal for forming a strong bond between the copper and the dielectric.
Yet this is in direct contrast with the requirements of a good transmission line, since the rough surface is then less than ideal for transmission of high-frequency EM waves. Conversely, a surface with a mirror-like finish on a perfectly smooth copper foil is inadequate for foil-to-dielectric adhesion. It’s a ‘Catch-22’.
Ultimately, fabricating PCBs with low-loss conductors while maintaining good adhesion between the dielectric material and copper depends on achieving a compromise in the surface composition of the copper foil.
Effect on Dielectric Constant
Another important factor involving the design and manufacture of PCBs is the relative permittivity of the dielectric material, commonly referred to as its dielectric constant, or Dk. In reality, Dk, rather than being a constant, varies with frequency.
The value of Dk, as the dielectric manufacturer’s data sheets will report, is often assumed to be an intrinsic property of the material. However, manufacturers generate the effective dielectric constant using a specific test method, sandwiching the dielectric material between two copper plates. When comparing simulation against measurements, there is often a discrepancy in insertion loss caused by increased phase delay, and this resulting from surface roughness.
The explanation is simply that surface roughness decreases the effective separation between the parallel plates, thereby increasing the electric field strength and leading to an increase in capacitance. This accounts for the increase in effective dielectric constant.
Laminate suppliers commonly use the Clamped Stripline Resonator Test to measure the effective dielectric constant of their material. The test is defined by IPC-TM-650 18.104.22.168c, and was widely adopted by the industry because it is repeatable, accurate, and fast. As the measurement is highly dependent on the test apparatus and the measuring conditions, it does not guarantee that the values are accurate for design applications. This is primarily because the copper foils used for the test are not physically bonded to the laminate, leaving small air gaps in between the layers, affecting the results.
Designers get around this mismatch during simulations by using a multiplication factor for the dielectric constant for their impedance calculations, rather than using the Dk factor directly.
Commercial PCB Laminates
Suppliers, recognizing the effect of surface roughness on performance at high frequencies, offer commercial laminates with copper foils in numerous profiles. They produce these laminates with different levels of copper treatment. For instance, they offer low profile (LP) copper conductors that provide excellent adhesion of the copper to the dielectric material, while the smooth conductor surface improves etch definition and reduces conductor losses.
Other suppliers offer materials with low profile, reverse-treated copper foils, which are ideal for high-frequency analog and digital circuits. They are supplied in a variety of panel sizes and standard dielectric thicknesses, with 0.5 or 1-oz. low profile, reverse-treated ED copper cladding. Two popular models of laminates have dielectric constants of 3.38 & 3.48 and dissipation factors of 0.0027 & 0.0037 in the Z-direction at 10 GHz. Both the materials are suitable for high-density circuits and are appropriate for low insertion loss, low passive intermodulation distortion, and excellent signal integrity.
Although special materials can help overcome the effects of conductor surface roughness at high frequencies, selecting a PCB material that minimizes the effects of surface roughness is not a simple task. When seeking to minimize the effects of surface roughness, materials with low profile copper foils will perform better with low conductor losses at higher frequencies, than materials with foils that feature higher profiles.
Contact the author at Rush PCB Inc.,
2149-20 O’Toole Ave., San Jose, CA 95131, U.S.A